VHDL Programming Exercises

Lecturer: Dr.-Ing. Ajoy K. Palit C1-Habilitand/Lehrer fuer Master Studiengang

Exercise 1

Constructing "AND", "OR", "NOT", "NAND", "NOR", "XOR" gates and "DRIVER" by using using "if-else-then" and "case-when" statements.

Exercise 2

"Signal" and "Variable" and Some of the "predefined types" in VHDL: "Bit", "Boolean", "Integer", "Real", "Character", "Time"

Exercise 3

Constructing "Full Adder" from "Half Adder" by using "Signals" and "wires".

Exercise 4

Constructing "(D-Type) flip-flop" and "Frequency Divider". Generate "Clock signal" by using "loop" keyword in Testbench.

Exercise 5

Component instantiation with "Generate" keyword and its application on "n-Stage Shift Register".

Exercise 6

"Functions" and "Procedures" and their application for "bit comparator".

Exercise 7

"VHDL Package" and its application for "bit comparator".

Exercise 8

"4 bits Nibble comparator" by using "Generate" keyword and your own "VHDL Package" for "functions" and "procedures".

Exercise 9

"JK flip-flop" and "4-bit couter using JK flip-flop"

Exercise 10

"Multiplexer " and "Demultiplexer"

Exercise 11

"BCD" to "excess-3 code converter"